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Last month, Micron disclosed its DRAM and NAND memory roadmaps for the next several years, revealing plans to use wafer bonding, new materials that enable making NAND cells smaller, High-NA EUV lithography, and detailing its moves toward 3D DRAM. Perhaps the most revealing part of Micron’s story is that the company plans to expand its portfolio of custom DRAM and NAND products as AI developers increasingly require memory and storage solutions optimized for their unique processor architectures and specific workloads.
“ DRAM is nearing atomic limits at this point: although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view,” said Scott DeBoer, president and chief technology and products officer at Micron, at the company’s event earlier this month. “[With 3D NAND, we are] really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward.”
DRAM: 4F2 cells axed, High-NA EUV lithography, new materials, and 3D DRAM enable future scaling
In a surprising move, Micron decided to abandon plans to produce DRAM with 4F2 memory cells, unlike its rivals at CXMT, Samsung, and SK hynix, citing the lack of a viable scaling path beyond where Micron is today. Instead, Micron’s roadmap for the coming years includes wafer bonding, High-NA EUV lithography, new materials, and eventually 3D DRAM. The company plans to begin mass production of its next-generation 1δ memory in the second half of 2027, while subsequent 1ε, ζÅ, and ηÅ technologies are at various stages of development. In parallel, Micron is developing two generations of 3D DRAM that could eventually succeed conventional planar memory.
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Micron’s current 1γ (1-gamma) DRAM process technology, which is in high-volume manufacturing (HVM), is the company’s first DRAM node to use EUV lithography. Previously, Micron had used multipatterning with DUV lithography and remained competitive with Samsung and SK hynix, which relied on EUV for critical layers.
Micron’s next-generation 1δ (1-delta) fabrication process is currently in the yield ramp stage and is scheduled to enter mass production in the second half of 2027. The company expects the technology to increase bit density by mid-20% compared to 1γ, while advanced high-k metal gate (HKMG) CMOS, new materials, angstrom-level process control, and equipment intelligence should improve performance, power efficiency, and ultimately yields as well as costs.
Micron plans to manufacture 1δ DRAM in the U.S. and use the technology for next-generation DDR, LPDDR, graphics memory, HBM5, vertical HBM (vHBM), and vertical Edge Inference Memory (vEIM) products. Meanwhile, to make HBM5, vHBM5, and vEIM products, the node will also support additional features like through-silicon vias (TSVs) and other elements to improve thermal performance.
The subsequent 1ε (1-epsilon) process will rely on wafer bonding, which will enable Micron to produce different structures on separate wafers and then bond them together. This approach could increase flexibility in memory design and manufacturing, but Micron has yet to disclose its plans to implement wafer bonding, which structures it will bond, or what improvements in density, performance, and power consumption the technology will provide. The process is currently under development, and there is no announced production schedule.
Micron’s ζÅ (zeta-angstrom) production node is currently in early development and will introduce High-NA EUV lithography to memory manufacturing, which will enable further reductions in critical dimensions. The company has not disclosed how many layers will require High-NA lithography, the expected density improvements, or when the technology will enter mass production. However, it is obvious that the node will not be here until at least 2030, years after Samsung and SK hynix adopt High-NA EUV at their DRAM fabs (planned for 2028).
The ηÅ (eta-angstrom) process represents the most distant generation on Micron’s disclosed planar DRAM roadmap and is currently in the pathfinding stage. After Micron inserts High-NA EUV lithography into its DRAM production flow, the company intends to bet on other methods of scaling. Although Micron mentions new materials, it hasn’t identified them or explained how they will affect device structures. These could include new photoresists, deposition precursors, dielectric materials, or conductive materials that would enable the company to manufacture smaller transistors and capacitors, and ultimately increase DRAM cell density.
In any case, Micron’s roadmap is focused on continuing development of DRAM based on 6F² cells, which differs from the plans of CXMT, Samsung, and SK hynix.
3D1 and 3D2: Transition to 3D DRAM is looming
In parallel with conventional DRAM development, Micron is working on two generations of 3D DRAM, currently called 3D1 and 3D2. Unlike planar DRAM, which primarily relies on smaller memory cells to increase bit density, 3D DRAM would use the vertical dimension to accommodate more memory cells within a given area. Micron intends to introduce the technology when it becomes competitive with conventional DRAM in terms of manufacturing costs and performance. The company has not disclosed architectures, layer counts, or density targets.
In fact, while Micron has outlined its future memory architectures through 2030, its DRAM manufacturing roadmap provides a firm production window only for the 1δ process, which is scheduled to enter high-volume manufacturing in the second half of 2027. The company has not disclosed production dates for subsequent planar DRAM nodes or either generation of 3D DRAM.
Custom HBM and vertical memory architectures
In addition to conventional DRAM, Micron plans to use its future manufacturing technologies for HBM4E, HBM5, HBM5E, and new vertically integrated memory architectures. Starting with HBM4E, the company will offer both standard and custom HBM products, which will be followed by custom HBM5E, vHBM, and vEIM (vertical Edge Inference Memory). All of these will mark the re-emergence of custom memory in mass-produced products.
Custom HBM4E (cHBM4E) will enable Micron’s customers to shrink memory I/O width and/or integrate additional logic into the memory’s base die to free up valuable die space for compute and optimize performance and power consumption for specific AI accelerators. According to Scott DeBoer, Micron’s president and chief technology and products officer, some of these functions would otherwise reside in the ASIC itself, so moving them closer to memory should improve overall system efficiency.
“When we co-design a base die, and the certain logic elements that are desired to be put in that base die are generally an offload from GPU circuitry anyway onto the base die to put it closer to the memory,” said DeBoer. “Moving what makes more sense onto the base die will still be a reality in [the] vertical HBM timeframe as well.”
To support these capabilities, Micron intends to use advanced foundry process technologies for the base dies of both standard and custom HBM products, although it has not disclosed specific nodes. For custom designs, the company will select the most cost-effective process that meets customer requirements. For example, Micron expects HBM4E to require more advanced CMOS technologies to meet its performance and power targets.
Further down the road, Micron intends to introduce vertical HBM (vHBM), which will stack memory directly on top of ASICs and CPUs rather than next to them on an interposer. This architecture promises substantially higher bandwidth, thanks to dense vertical connections (as well as significantly lower latencies) thanks to adjacent placement, but it is also set to create considerable challenges related to power delivery and heat dissipation. To address them, Micron plans to use hybrid bonding for advanced interconnects, integrated heat spreaders, and thermally aware designs. Interestingly, the company expects conventional HBM and vHBM to coexist in some designs, where vHBM provides maximum bandwidth, while traditional HBM serves capacity requirements.
Another technology under development is vertical Edge Inference Memory (vEIM), which shares many of its packaging and integration technologies with HBM, but targets applications that require power efficiency more than maximum bandwidth. Micron’s 1st Generation vEIM aims to deliver formidable HBM4-like 2 TB/s of bandwidth while consuming less than 1 picojoule per bit of data transfer energy.
Both architectures will require close cooperation with customers to optimize memory, logic, packaging, and thermal characteristics for particular applications, so Micron will need to work with its clients to make vHBM and vEIM successful. Interestingly, Micron’s customer-specific development efforts extend beyond HBM and EIM.
For example, the company is collaborating with Meta to optimize LPDDR6 for data center applications, which primarily include reliability, serviceability, and availability. Micron expects LPDDR6 to reduce power consumption by approximately 35% compared to LPDDR5, which will be very important for dense memory deployments. The company also intends to develop DDR6 — which targets 2X DDR5 bandwidth — in cooperation with major customers to better understand and ultimately meet their needs.
Speaking of customer cooperation, DeBoer stresses that Micron now collaborates with customers from the earliest stages of product definition through joint design, development, validation, and volume production. According to the executive, this approach differs substantially from how the company worked with customers previously.
“Across our AI co-invention opportunities we are co-imagining, co-designing, co-developing, co-validating, and then delivering at scale,” DeBoer said. “This opportunity is truly unique. It is very different than the way we interacted with customers even three or four years ago.”
Advanced CMOS: More than 10X performance improvement
In addition to shrinking DRAM cells and developing vertical memory architectures, Micron is developing advanced CMOS technologies for peripheral circuitry. The company’s roadmap includes several generations of DRAM CMOS logic with high-k metal gate transistors, followed by 1st and 2nd Generation 3D CMOS technologies.
Micron expects these advances to increase its CMOS logic performance by more than 10X between 2020 and 2030, which should help the company address the growing bandwidth and power requirements of AI-oriented memory products.
3D NAND: From next-gen 400L 3D NAND to AI-oriented NAND
Although Micron’s event was mostly dedicated to the future of DRAM, the company also shared some details about its upcoming NAND innovations, which include 11th Generation 3D NAND with 400 layers, post-G11 3D NAND, and AI-oriented NAND memory that either offers high bandwidth or high IOPS.
Micron’s next-generation G11 (N170) 3D NAND technology represents a substantial departure from its current G9 (N160) process. The company plans to increase the number of active memory layers from 276 to more than 400, introduce wafer-on-wafer bonding, and implement an industry-leading memory cell pitch.
These improvements are expected to double the bit density of G11 3D NAND compared with G9 3D NAND, presumably from 21 Gb/mm2 to 42 Gb/mm2 in the case of 3D TLC devices, which should substantially reduce manufacturing costs per bit once the technology reaches mature yields.
In addition to increased storage density, G11 also targets a 50% increase in I/O speed compared with G9, which implies a potential transfer rate of approximately 5,400 MT/s. Furthermore, Micron expects to reduce data transfer energy consumption by more than 25% per bit, an important improvement for high-capacity SSDs and AI storage systems that tend to move huge amounts of data.
One of the most important changes with G11 is the adoption of wafer-on-wafer bonding, which lets Micron manufacture memory arrays and the periphery and I/O circuits on another wafer, then bond them together. Chinese manufacturer YMTC has used this method to maximize storage capacity and performance, so it is not surprising that Micron and other memory manufacturers are adopting the technique as well.
Micron expects to start mass production of G11 3D NAND in the second half of 2027.
Improving 3D NAND past G11: New materials and further XYZ scaling
Micron intends to continue improving 3D NAND beyond 11th Generation through a combination of new materials, denser memory cell architectures, and more energy-efficient devices and data paths. Specifically, Micron is investigating high-mobility materials that could improve the electrical characteristics of future memory devices, as well as ultra-dense cell architectures intended to increase storage density beyond what an increase in active layers provides.
Meanwhile, more energy-efficient circuitry and data paths should help offset the growing power consumption associated with higher NAND capacities and faster interfaces.
“Beyond G11, we have a strong roadmap, not going to go into great detail on it today, but really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward,” said DeBoer. “[…] The current industry direction and Micron’s direction is scaling both by adding layers [and] also by shrinking the cell dimensions.”
The company has not identified the materials it intends to introduce or explained how they will affect memory cell structures. Nor has it provided quantitative density, performance, or power targets for NAND generations beyond G11.
AI-oriented NAND: Higher IOPS and bandwidth
Although Micron is not ready to share details about its G12 or G13 3D NAND generations, the company disclosed that it is developing two specialized NAND architectures for AI applications.
The first — High-IOPS AI NAND — architecture focuses on maximum random I/O performance and uses SLC-based designs with small blocks to accelerate workloads such as vector searches, graph analytics, and AI context management. Micron envisions products capable of delivering approximately 25 million to 100 million IOPS, depending on their configuration, and expects to bring products based on this approach to market over the next couple of years.
The second — High-Bandwidth AI NAND — architecture prioritizes bandwidth over random I/O performance. Micron is investigating vertically stacked NAND devices connected through TSVs and equipped with a logic base die that resides close to AI accelerators, so from many points of view this concept resembles SanDisk’s HBF. However, Micron does not believe that simply placing NAND stacks alongside AI accelerators on an interposer offers sufficient advantages. Instead, the company is exploring alternative integration approaches that bring NAND closer to compute resources, but don’t necessarily consume valuable shoreline (the perimeter, or edge) of AI accelerators.
“[The High-Bandwidth AI NAND is] more costly and has to be implemented in partnership with customers in a way to ensure that they are meeting the mark and the cost point to drive the value proposition,” DeBoer said. “We are enabling TSV-stacked NAND with a logic base die to bring memory closer to accelerators. We do not think placing it along the shoreline of the GPU has merit. Instead, we want to position it closer to the compute itself to take advantage of this high-performance NAND.”
These specialized AI-focused NAND architectures will complement Micron’s conventional SSD roadmap, which includes plans for drives with capacities of up to 512 TB in the foreseeable future.